Microelectronic devices, such as semiconductors or integrated circuits, can include millions of electronic circuit devices such as transistors, capacitors, etc. To further increase the density of devices found on integrated circuits, even smaller feature sizes are desired. To achieve these smaller feature sizes, the size of conductive lines, vias, interconnects, gates, etc., must be reduced. Reliable formation of multilevel interconnect structures is also necessary to increase circuit density and quality. Advances in fabrication techniques have enabled use of copper for conductive lines, interconnects, vias, and other structures. However, electromigration in interconnect structures becomes a greater hurdle to overcome, with decreased feature size and the increased use of copper for interconnections.
With the continued shrinking of critical dimensions, the need for a single layer barrier/liner for back end of line interconnect is necessary. Traditionally, a deposition of the barrier followed by a liner has been used extensively in the BEOL in the form of TaN/Ta and TaN/Co. However, the use of a multilayer approach is becoming ineffective as the feature sizes of the interconnects are becoming too small to allow for multiple layers. Therefore, there is a need in the art for single layer barrier films using a deposition technique that can conformally coat a high aspect ratio small feature trench or hole.